rev. a C2C ad767Cspecifications (t a = +25 8 c, 6 15 volt power supplies, unipolar mode, unless otherwise noted.) model ad767j/a/s 1 ad767k/b ad767a 2 chips min typ max min typ max min typ max units digital inputs resolution 12 12 12 bits logic levels (ttl compatible, t min Ct max ) 3 v ih (logic 1) +2.0 +5.5 +2.0 +5.5 +2.0 +5.5 v v il (logic 0) j, k, a, b 0 +0.8 0 +0.8 0 +0.8 v v il (logic 0) s 0 +0.7 v i ih (v ih = 5.5 v) 3 10 3 10 3 10 m a i il (v il = 0.8 v) 1 5 1 5 1 5 m a transfer characteristics accuracy linearity error @ +25 c 1/2 6 1 1/8 6 1/2 1/2 6 1 lsb t a = t min to t max 1/2 6 1 1/4 6 1/2 1/2 6 1 lsb differential linearity error @ +25 c 1/2 6 1 1/4 6 1 1/2 6 1 lsb t a = t min to t max monotonicity guaranteed monotonicity guaranteed monotonicity guaranteed lsb gain error 4 0.1 6 0.2 0.1 6 0.2 0.1 6 0.2 % of fsr 5 unipolar offset error 4 1 6 2 1 6 2 1 6 2 lsb bipolar zero error 4 0.05 6 0.1 0.05 6 0.1 0.05 6 0.1 % of fsr drift gain t a = 25 c to t min or t max 5 30 5 15 5 30 ppm of fsr/ c unipolar offset t a = 25 c to t min or t max 1 3 1 3 1 3 ppm of fsr/ c bipolar zero t a = 25 c to t min or t max 5 10 10 5 10 ppm of fsr/ c conversion speed settling time to 0.01% of fsr for fsr change (2 k w|| 500 pf load) with 10 k w feedback 3 4 3 4 3 4 m s with 5 k w feedback 2 3 2 3 2 3 m s for lsb change 1 1 1 m s slew rate 10 10 10 v/ m s analog output ranges 6 2.5, 5, 10, 2.5, 5, 10, 2.5, 5, 10, v +5, +10 +5, +10 +5, +10 output current 5 5 5ma output impedance (dc) 0.05 0.05 0.05 w short-circuit current 40 40 40 ma reference output 9.90 10.00 10.10 9.90 10.00 10.10 9.90 10.00 10.10 v external current 0.1 1.0 0.1 1.0 0.1 1.0 ma power supply sensitivity v cc = +11.4 to +16.5 v dc 5 10 5 10 5 10 ppm of fs/% v ee = C11.4 to C16.5 v dc 5 10 5 10 5 10 ppm of fs/% power supply requirements rated voltages 12, 15 12, 15 12, 15 v range 6 6 11.4 6 16.5 6 11.4 6 16.5 6 11.4 6 16.5 v supply current +11.4 to +16.5 v dc 9 13 9 13 9 13 ma C11.4 to C16.5 v dc 18 23 18 23 18 23 ma total power consumption 400 600 400 600 400 600 mw temperature range j/k 0 +70 0 +70 c a/b C25 +85 C25 +85 C25 +85 c s C55 +125 C55 +125 c operating C55 +125 C55 +125 c storage (all grades) C65 +125 C65 +125 C65 +125 c notes 1 ad767 s specifications shown for information only. consult analog devices military databook or contact factory for a controlled specification sheet. 2 ad767a chips specifications are tested at +25 c and, when in boldface, at +85 c. they are typical at C25 c. 3 the digital input specifications are 100% tested at +25 c, and guaranteed but not tested over the full temperature range. 4 adjustable to zero. 5 fsr means full-scale range and is 20 v for 10 v range and 10 v for the 5 v range. 6 a minimum power supply of 12.5 v is required for a 10 v full-scale output and 11.4 v is required for all other voltage ranges. specifications subject to change without notice. specifications shown in boldface are tested on all production units at final electrical test (except per notes 1 and 2). results from those tests are used to calculate outgoing quality levels. all min and max specifications are guaranteed, although only those shown in boldface are tested on all production units.
ad767 rev. a C3C absolute maximum ratings* v cc to power ground . . . . . . . . . . . . . . . . . . . . .0 v to +18 v v ee to power ground . . . . . . . . . . . . . . . . . . . . . 0 v to C18 v digital inputs (pins 11, 13C24) to power ground . . . . . . . . . . . . . . . . . . . . C1.0 v to +7.0 v ref in to reference ground . . . . . . . . . . . . . . . . . . . . . . 12 v bipolar offset to reference ground . . . . . . . . . . . . . . . . 12 v 10 v span r to reference ground . . . . . . . . . . . . . . . . . 12 v 20 v span r to reference ground . . . . . . . . . . . . . . . . . 24 v ref out, v out (pins 6, 9) . . . indefinite short to power ground momentary short to v cc power dissipation . . . . . . . . . . . . . . . . . . . . . . . . . . . 1000 mw *stresses above those listed under absolute maximum ratings may cause permanent damage to the device. this is a stress rating only and functional operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. exposure to absolute maximum rating conditions for extended periods may affect device reliability. timing specifications (all models, t a = 25 c, v cc = +12 v or +15 v, v ee = C12 v or C15 v) symbol parameter min typ max t ds data valid to end of cs 40 C C ns (C25 c to +85 c) 60 C C ns (C55 c to +125 c) 90 C C ns t dh data hold ti?ne 10 C C ns (C25 c to +85 c) 10 C C ns (C55 c to +125 c) 20 C C ns t cs cs pulse width 40 C C ns (C25 c to +85 c) 60 C C ns (C55 c to +125 c) 90 C C ns t sett output voltage settling time* C 2 4 m s *t sett is measured referenced to the leading edge of t cs . if t cs > t ds , then t sett is measured referenced to the beginning of data valid. pin configuration plcc dip ordering guide linearity gain t.c. temperature error max max model 1 package range 8 ct min Ct max ppm/ 8 c ad767jn plastic dip 0 to +70 1 lsb 30 ad767jp plcc 0 to +70 1 lsb 30 ad767kn plastic dip 0 to +70 1/2 lsb 15 ad767kp plcc 0 to +70 1/2 lsb 15 ad767ad ceramic dip C25 to +85 1 lsb 30 ad767bd ceramic dip C25 to +85 1/2 lsb 15 ad767sd/ 883b ceramic dip C55 to +125 note 2 note 2 ad767a chips n/a C25 to +85 1 lsb 30 notes 1 d = ceramic dip; n = plastic dip; p = plastic leaded chip carrier. 2 for details on grade and package offerings screened in accordance with mil-std-883, refer to the analog devices military products databook or current ad767/883b data sheet.
ad767 rev. a C4C the ad767 offers true 12-bit performance over the full temperature range linearity error: analog devices defines linearity error as the maximum deviation of the actual, adjusted dac output from the ideal analog output (a straight line drawn from 0 to f.s. C 1 lsb) for any bit combination. this is also referred to as relative accuracy. the ad767 is laser trimmed to typically maintain linearity errors at less than 1/8 lsb for the k and b versions and 1/2 lsb for the j, a and s versions. linearity over temperature is also held to 1/2 lsb (k/b) or 1 lsb (j/a/s). monotonicity: a dac is said to be monotonic if the output either increases or remains constant for increasing digital inputs such that the output will always be a nondecreasing function of input. all versions of the ad767 are monotonic over their full operating temperature range. differential nonlinearity: monotonic behavior requires that the differential linearity error be less than 1 lsb both at +25 c as well as over the temperature range of interest. differential nonlinearity is the measure of the variation in analog value, normalized to full scale, associated with a 1 lsb change in digital input code. for example, for a 10 volt full-scale output, a change of 1 lsb in digital input code should result in a 2.44 mv change in the analog output (1 lsb = 10 v 3 1/4096 = 2.44 mv). if in actual use, however, a 1 lsb change in the input code results in a change of only 0.61 mv (1/4 lsb) in analog output, the differential nonlinearity error would be C1.83 mv, or C3/4 lsb. gain error: dac gain error is a measure of the difference between an ideal dac and the actual devices output span. all grades of the ad767 have a maximum gain error of 0.2% fs. however, if this is not sufficient, the error can easily be adjusted to zero (see figures 2 and 3). unipolar offset error: unipolar offset error is a combination of the offset errors of the voltage-mode dac and the output amplifier and is measured when the ad767 is configured for unipolar outputs. it is present for all codes and is measured with all 0s in the dac latches. this is easily adjustable to zero when required. bipolar zero error: bipolar zero errors result from errors produced by the dac and output amplifier when the ad767 is configured for bipolar output. again, as with unipolar offset and gain errors, this is easily adjusted to zero when required. analog circuit connections internal scaling resistors provided in the ad767 may be connected to produce bipolar output voltage ranges of 10, 5 or 2.5 v or unipolar output voltage ranges of 0 to +5 v or 0 to +10 v. gain and offset drift are minimized in the ad767 because of the thermal tracking of the scaling resistors with other device components. connections for various output voltage ranges are shown in table i. figure 1. output amplifier voltage range scaling circuit unipolar configuration (figure 2) this configuration will provide a unipolar 0 to +10 volt output range. in this mode, the bipolar offset terminal, pin 4, should be grounded if not used for trimming. step i zero adjust turn all bits off and adjust zero trimmer r1, until the output reads 0.000 volts (1 lsb = 2.44 mv). in most cases this trim is not needed, and pin 4 should be connected to pin 5. step ii gain adjust turn all bits on and adjust 100 w gain trimmer r2 until the output is 9.9976 volts. (full scale is adjusted to 1 lsb less than nominal full scale of 10.000 volts.) figure 2. 0 to +10 v unipolar voltage output table i. output voltage range connections output digital connect connect connect connect range input codes pin 9 to pin 1 to pin 2 to pin 4 to 10 v offset binary 1 9 nc 6 (through 50 w fixed or 100 w trim resistor) 5 v offset binary 1 and 2 2 and 9 1 and 9 6 (through 50 w fixed or 100 w trim resistor) 2.5 v offset binary 2 3 9 6 (through 50 w fixed or 100 w trim resistor) 0 to +10 v straight binary 1 and 2 2 and 9 1 and 9 5 (or optional trim C see figure 2) 0 to +5 v straight binary 2 3 9 5 (or optional trim C see figure 2)
ad767 rev. a C5C bipolar configuration (figure 3) this configuration will provide a bipolar output voltage from C5.000 to +4.9976 volts, with positive full scale occurring with all bits on (all 1s). step i offset adjust turn off all bits. adjust 100 w trimmer r1 to give C5.000 volts output. step ii gain adjust turn on all bits. adjust 100 w gain trimmer r2 to give a reading of +4.9976 volts. step iii bipolar zero adjust (optional) in applications where an accurate zero output is required, set the msb on, all other bits off, and readjust r1 for zero volts output. figure 3. 5 v bipolar voltage output internal/external reference use the ad767 has an internal low-noise buried zener diode reference which is trimmed for absolute accuracy and tempera- ture coefficient. this reference is buffered and optimized for use in a high-speed dac and will give long-term stability equal or superior to the best discrete zener reference diodes. the per- formance of the ad767 is specified with the internal reference driving the dac since all trimming and testing (especially for full-scale error and bipolar offset) is done in this configuration. the internal reference has sufficient buffering to drive external circuitry in addition to the reference currents required for the dac (typically 0.5 ma to ref in and 1.0 ma to bipolar offset). a minimum of 0.1 ma is available for driving external loads. the ad767 reference output should be buffered with an external op amp if it is required to supply more than 0.1 ma output current. the reference is typically trimmed to 0.2%, then tested and guaranteed to 1.0% max error. the temperature coefficient is comparable to that of the full-scale tc for a particular grade. if an external reference is used (10.000 v, for example), additional trim range must be provided, since the internal reference has a tolerance of 1%, and the ad767 full-scale and bipolar offset are both trimmed with the internal reference. the gain and offset trim resistors give about 0.25% adjustment range, which is sufficient for the ad767 when used with the internal reference. it is also possible to use external references other than 10 volts. the recommended range of reference voltage is from +8 to +10.5 volts, which allows both 8.192 v and 10.24 v ranges to be used. the ad767 is optimized for fixed-reference applications. if the reference voltage is expected to vary over a wide range in a particular application, a cmos multiplying dac is a better choice. reduced values of reference voltage will also permit the 12 volt 5% power supply requirement to be relaxed to 12 volts 10%. it is not recommended that the ad767 be used with external feedback resistors to modify the scale factor. the internal resistors are trimmed to ratio-match and temperature-track the other resistors on the chip, even though their absolute tolerances are 20%, and absolute temperature coefficients are approximately C50 ppm/ c. if external resistors are used, a wide trim range ( 20%) will be needed and temperature drift will be increased to reflect the mismatch between the temperature coefficients of the internal and external resistors. small resistors may be added to the feedback resistors in order to accomplish small modifications in the scaling. for example, if a 10.24 v full scale is desired, a 140 w 1% low-tc metal-film resistor can be added in series with the internal (nominal) 5k feedback resistor, and the gain trim potentiometer (between pins 6 and 7) should be increased to 200 w . in the bipolar mode, increase the value of the bipolar offset trim potentiometer also to 200 w . figure 4. using the ad767 with the ad588 high precision reference
ad767 rev. a C6C using the ad767 with the ad588 high precision voltage reference the ad767 is specified for gain drift from 15 ppm/ c to 30 ppm/ c (depending on grade) using its internal 10 volt reference. since the internal reference contributes the majority of this drift, an external high-precision voltage reference will greatly improve performance over temperature. as shown in figure 4, the 10 volt output from the ad588 is used as the reference. with a 1.5 ppm/ c output voltage drift the ad588 contributes less than 1/2 lsb gain drift when used with the ad767 over the industrial temperature range. using this combination may result in apparent increases in full-scale error due to the differences between the internal reference by which the device is laser trimmed and the external reference with which the device is actually applied. the ad767 internal reference is specified to be 10 volts 100 mv whereas the ad588 is specified as 10 volts 1 mv. this may result in up to 101 mv of apparent full-scale error beyond the 25 mv specified ad767 gain error. the 500 w potentiometer in series with the reference input allows adequate trim range to null this error. grounding rules the ad767 brings out separate analog and power grounds to allow optimum connections for low noise and high-speed performance. these grounds should be tied together at one point, usually the device power ground. the separate ground returns are provided to minimize current flow in low-level signal paths. the analog ground at pin 5 is the ground point for the output amplifier and is thus the high quality ground for the ad767; it should be connected directly to the analog reference point of the system. the power ground at pin 12 can be connected to the most convenient ground point; analog power return is preferred. if power ground contains high frequency noise beyond 200 mv, this noise may feed through the converter, thus some caution will be required in applying these grounds. it is also important to apply decoupling capacitors properly on the power supplies for the ad767. the correct method for decoupling is to connect a capacitor from each power supply pin of the ad767 to the analog ground pin of the ad767. any load driven by the output amplifier should also be referred to the analog ground pin. optimizing settling time the dynamic performance of the ad767s output amplifier can be optimized by adding a small (20 pf) capacitor across the feedback resistor. figure 5 shows the improvement in both large-signal and small-signal settling for the 10 v range. in figure 5a, the top trace shows the data inputs (db11Cdb0 tied together), the second trace shows the cs pulse, and the lower two traces show the analog outputs for c f = 0 and 20 pf respectively. figure 5a. large scale settling figures 5b and 5c show the settling time for the transition from all bits on to all bits off. note that the settling time to 1/2 lsb for the 10 v step is improved from 2.4 microseconds to 1.6 microseconds by the addition of the 20 pf capacitor. figure 5b. fine-scale settling, c f = 0 pf figure 5c. fine-scale settling, c f = 20 pf figures 5d and 5e show the settling time for the transition from all bits off to all bits on. the improvement in settling time gained by adding c c = 20 pf is similar. figure 5d. fine-scale settling, c f = 0 pf
ad767 rev. a C7C figure 5e. fine-scale settling, c f = 20 pf digital input considerations the threshold of the digital input circuitry is set at 1.4 volts and does not change with supply voltage. thus the ad767 digital interface may be driven with any of the popular types of 5 volt logic. a good engineering practice is to connect unused inputs to power ground to improve noise immunity. unconnected data and control inputs will float to logic 0 if left open. the low digital input current of the ad767 eliminates the need for buffer/drivers required by many monolithic converters using bipolar technology. a single low-power schottky gate, for example, will drive several ad767s when connected to a common bus. input coding the ad767 uses positive-true binary input coding. logic 1 is represented by an input voltage greater than 2.0 v, and logic 0 is defined as an input voltage less than 0.8 v. unipolar coding is straight binary, where all zeroes (000 h ) on the data inputs yields a zero analog output and all ones (fff h ) yields an analog output 1 lsb below full scale. bipolar coding is offset binary, where an input code of 000 h yields a minus full-scale output, an input of fff h yields an output 1 lsb below positive full scale, and zero occurs for an input code with only the msb on (800 h ). the ad767 can be used with twos complement input coding if an inverter is used on the msb (db11). microprocessor interface the ad767, with its 40 ns minimum cs pulse width, may be easily interfaced to any of todays high-speed microprocessors. the 12-bit single buffered input register will accept 12-bit parallel data from processors such as the 68000, 8086, tms320 series, and the analog devices adsp-2100. several illustrative examples follow. 68000 C ad767 interface figure 6 illustrates the ad767 interface to a 68000 micro- processor. an active low decoded address is ored with the processors r/ w signal to provide cs and latch data into the ad767. later in the bus cycle the processor issues the upper ( uds ) and lower ( lds ) data strobes which are gated with the decoded address to provide dtack and terminate the bus cycle. as shown, this interface will support a 12.5 mhz 68000 system. figure 6. 68000 C ad767 interface 8086 C ad767 interface interfacing the ad767 to the 8086 16-bit microprocessor requires a minimal amount of external components. a 10 mhz 8086, for example, generates a 165 ns low write pulse which may be gated with a decoded address to provide cs for the ad767. as wr returns high valid data is latched into the dac. see figure 7. figure 7. 8086 C ad767 interface tms32010 C ad767 interface the high-speed digital interface of the ad767 facilitates its use with the tms32010 microprocessor at speeds up to 20 mhz. in the three multiplexed lsbs of the address bus, pa2 C pa0 are decoded as a port address and ored with the low write enable to generate cs for the dac. a simple out xx,y instruction will output the data word stored in memory location xx to any one of eight port locations y. figure 8. tms32010 C ad767 interface tms32020 C ad767 interface interfacing the ad767 to the tms32020 microprocessor is easily achieved by using the tms32020 i/o port capability. the is signal distinguishes the i/o address space from the local program/data memory space and is used to enable a 74ls138 decoder. the decoded port address is then gated with the r/ w and strb signals to provide the ad767 cs .
ad767 rev. a C8C c1068aC10C4/88 printed in u.s.a. figure 9. tms32020 C ad767 interface adsp-2100 C ad767 interface the adsp-2100 single chip dsp processor may be interfaced to the ad767 as shown in figure 10. with a clock frequency of 32 mhz, and instruction execution in a single 125 ns cycle, the processor will support the ad767 interface with a single wait state. figure 10. adsp-2100 C ad767 interface at the beginning of the data memory access cycle the processor provides a 14-bit address on the dma bus. the dms signal is then asserted enabling a low address decode. valid data is now placed on the data bus and dmwr is issued. dmwr is ored with the low address decode to generate the ad767 cs . the low decoded address is also gated with the q output of a d flip-flop to hold dmack (data memory acknowledge) low. this forces the processor into a wait state and extends the ad767 cs by 1 clock cycle. the rising edge of clkout latches q high bringing dmack high. the cycle is now complete. tms320c25 C ad767 interface figure 11 illustrates the ad767 interface to a tms320c25 digital signal processor. due to the high-speed capability of the processor (40 mhz), a single wait state is required and is easily generated using msc. a 20 mhz tms320c25 however, does not require wait states and should be interfaced using the circuit shown in figure 9. figure 11. tms320c25 C ad767 interface outline dimensions dimensions shown in inches and (mm). 24-pin ceramic (suffix d) 24-pin plastic (suffix n) 28-pin plcc (suffix p)
|
